SCMOS Layout Rules - Simple Contact to Poly

On 0.5um process (and all finer feature size processes), it is required that ALL features on the insulator layers (CONTACT, VIA, VIA2) MUST BE of the single standard size; there are no exceptions for pads (or logos, or anything else); large openings must be replaced by an array of standard sized openings.
 
Rule Description Lambda
5.1 Exact contact size 2 x 2
5.2 Minimum poly overlap 1.5
5.3 Minimum contact spacing 2
[SUBM 3]
5.4 Minimum spacing to gate of transistor 2

 


SCMOS Layout Rules - Simple Contact to Active

Rule Description Lambda
6.1 Exact contact size 2 x 2
6.2 Minimum active overlap 1.5
6.3 Minimum contact spacing 2
[SUBM 3]
6.4 Minimum spacing to gate of transistor 2

 


SCMOS Layout Rules - Alternative Contact to Poly

The rules above are preferred. If, however, one cannot handle the 1.5 lambda contact overlap in 5.2, then that rule, 5.2, may be replaced by these rules, which reduce the overlap, but increase the spacing to surrounding features. The remaining rules above, 5.1, 5.3, and 5.4, still apply as originally stated.
 
Rule Description Lambda
5.2.b Minimum poly overlap 1
5.5.b Minimum spacing to other poly 4
[SUBM 5]
5.6.b Minimum spacing to active (one contact) 2
5.7.b Minimum spacing to active (many contacts) 3

 


SCMOS Layout Rules - Alternative Contact to Active

The rules above are preferred. If, however, one cannot handle the 1.5 lambda contact overlap in 6.2, then that rule, 6.2, may be replaced by these rules, which reduce the overlap, but increase the spacing to surrounding features. The remaining rules above, 6.1, 6.3, and 6.4, still apply as originally stated.
 
Rule Description Lambda
6.2.b Minimum active overlap 1
6.5.b Minimum spacing to diffusion active 5
6.6.b Minimum spacing to field poly (one contact) 2
6.7.b Minimum spacing to field poly (many contacts) 3
6.8.b Minimum spacing to poly contact 4